Freescale Semiconductor /MKW21Z4 /XCVR_ANALOG_REGS /RX_AUXPLL

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Interpret as RX_AUXPLL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BIAS_TRIM 0 (DIAGSEL1)DIAGSEL1 0 (DIAGSEL2)DIAGSEL2 0LF_CNTL 0SPARE0VCO_DAC_REF_ADJUST 0 (VTUNE_TESTMODE)VTUNE_TESTMODE 0 (0)RXTX_BAL_BIAST 0RXTX_BAL_SPARE 0 (RXTX_RCCAL_DIAGSEL)RXTX_RCCAL_DIAGSEL

RXTX_BAL_BIAST=0

Description

RF Analog Aux PLL Control

Fields

BIAS_TRIM

rmap_rxtx_auxpll_bias_trim[2:0]

DIAGSEL1

rmap_rxtx_auxpll_diagsel1

DIAGSEL2

rmap_rxtx_auxpll_diagsel2

LF_CNTL

rmap_rxtx_auxpll_lf_cntl[2:0]

SPARE

rmap_rxtx_auxpll_spare[3:0]

VCO_DAC_REF_ADJUST

rmap_rxtx_auxpll_vco_dac_ref_adjust[3:0]

VTUNE_TESTMODE

rmap_rxtx_auxpll_vtune_testmode

RXTX_BAL_BIAST

rmap_rxtx_bal_biast[1:0]

0 (0): 0.6

1 (1): 0.4

2 (2): 0.9

3 (3): 1.2

RXTX_BAL_SPARE

rmap_rxtx_bal_spare[2:0]

RXTX_RCCAL_DIAGSEL

rmap_rxtx_rccal_diagsel

Links

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